The process of fabricating an integrated circuit includes material preparation, circuit fabrication, wafer-probe testing, assembly, final testing and shipment. Initially a silicon ingot is cut to create individual wafers. This group of wafers are commonly referred to as a ‘lot,’ whereby each wafer is referred to by lot number, wafer number, resistivity, etc. Circuit fabrication may include several subsequent steps of diffusion, ion implantation, photolithography and plasma etch. Typical integrated circuit fabrication processes include deposition and growth of a thin film on the surface of the wafer, transferring a circuit pattern to a masking layer on the film, removing areas of the film not protected by the masking layer and doping exposed areas of the wafer. These steps may be repeated depending upon the process, whether bipolar, MOS, CMOS or BiCMOS. Each one of these processes, as well as other factors such as handling, inherent crystal defects, or misprocessing, can produce a defect resulting in a device failure. Once each individual circuit or die is complete, it will be tested by a wafer probe to evaluate its functionality. The purpose of wafer-probe testing is two-fold: to identify and discard non-functional devices before they are subjected to costly back-end processes; and to gain information regarding fabrication process parameters so that problems can be identified and corrected on a timely basis.
Although the level of automation differs from system to system, almost all wafer-probe systems are programmable. Test data is typically transmitted to a tester controller database. The key components of a typical wafer-probe system include a microprocessor based tester controller, a tester module or subsystem comprising one or more pin cards, a probe card, and a prober. One or more microprocessors control the tester module and prober as well as serve to provide data collection, storage and transmission. The tester module, and its constituent pin cards, generates the input voltages, currents, and waveforms required to test the device. The tester module also measures voltages, currents and waveforms output from the device. The prober is the system component that actually handles the wafers. The prober moves the wafers in the x and y directions to align bonding pads of each die with the probe pin tips. It then raises the wafer to make contact with the probe tips and lowers the wafer after testing each die. The probe card is a printed circuit board or other assembly that holds the actual probe tips. The interface extending between the testing module and the prober is a cable interface.
The actual testing of the devices is software-driven in a sequence that includes continuity testing, functional testing, and parametric testing. Continuity testing is a very basic test to check whether a device turns on, if it is shorted, or if it has other fundamental flaws. Functional testing is a little more complicated than the continuity test. It tests whether the device works as a functional block. Parametric testing is the final and most complex test of the device. This test checks for device performance within the given specifications. The data is stored in a tester database associated with the tester controller. The results of the tests and the selected sorting algorithm determine if the device is functional, as well as which bin the device should be categorized in. Because the circuitry and performance characteristics of each device type is unique, each device type will usually require a unique testing program customized to measure the most relevant parameters. Accordingly, for a large family of devices and device types, a large number of testing programs exist.
Traditional automatic test equipment (ATE) incorporates expensive, high performance pattern memory sub-systems to deliver complex test patterns to the devices. These subsystems are designed to deliver wide patterns (typically 128 to 1024 bits) at high speeds (typically 20 to 100's MHz, more than 300 MHz on new devices). The depth of the pattern storage is typically 1 to 64 million. The width, speed and depth of the pattern memory requirements, along with the sequencing capability (loops, branches, etc.) combine to significantly affect the cost of the pattern subsystem, to the extent that most pattern subsystems represent a significant component of the overall ATE cost.
The traditional pattern memory subsystem limitations are often the source of test program development problems and initial design debug inefficiencies. The number of test patterns required is proportional to the number of transistors in a device. As the device integration rapidly progresses in accordance with Moore's Law, the corresponding test pattern requirements will present increasingly difficult challenges for cost-effective traditional pattern memory subsystems.
The goal of avoiding an expensive burn-in procedure and replacing it by a low-cost, fast, reliable and flexible procedure has been difficult to achieve. Accordingly, a need has arisen for a coherent approach to both a low-cost method and a low-cost testing equipment offering a fundamental solution not only to avoid burn-in, but to guarantee quality and reliability of semiconductor devices in general, and to achieve these goals with testers of much reduced cost. The method should be flexible enough to be applied for different semiconductor product families and a wide spectrum of design and process variations and should lend itself as a guiding tool during wafer fab processing as well as after testing at multiprobe and after assembly and packaging. The method and the testers should increase manufacturing throughput and save floor space, time and energy. In addition, to improve the throughput and thereby reduce the cycletime of testing steps, the testing method and apparatus should have the ability to simultaneously test multiple devices.
Many of the problems associated with costly testing equipment have been addressed by the testing method and apparatus described in U.S. patent application Ser. No. 09/413,926 entitled “Testing Method and Apparatus Assuring Semiconductor Device Quality and Reliability,” which has a filing date of Oct. 7, 1999 and which is hereby incorporated by reference into this application. To date, however, the method and apparatus described in this patent application has not been utilized to perform simultaneous testing of multiple devices.